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authorAurelien Jarno <aurelien@aurel32.net>2009-11-22 13:22:54 +0100
committerAurelien Jarno <aurelien@aurel32.net>2009-11-22 14:12:19 +0100
commit2a6e32dd46967124f12c29eece7aa7fc3f0ee063 (patch)
treefa0760fd31f33d71b3a52c3c90d056ce31adc5c6 /target-mips/cpu.h
parent5499b6ffac490a3a44dcb97e9cebb99f0151d696 (diff)
target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write, and the returned value can be shifted by a variable amount of bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 45f3987317..5287e9a90f 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -376,6 +376,8 @@ struct CPUMIPSState {
target_ulong llval;
target_ulong llnewval;
target_ulong llreg;
+ target_ulong CP0_LLAddr_rw_bitmask;
+ int CP0_LLAddr_shift;
target_ulong CP0_WatchLo[8];
int32_t CP0_WatchHi[8];
target_ulong CP0_XContext;