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authorAlistair Francis <alistair.francis@xilinx.com>2015-07-23 08:13:56 -0700
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2015-10-01 17:55:36 -0700
commit5250ced83173c9534b4a2723b7a50b67b7c7a6ee (patch)
tree4c23c9e1572e04cb300de6b0f5a5815e1839c761 /target-microblaze/cpu.c
parentc8667283a070d810f7917d69ea84209475c6e75e (diff)
downloadqemu-arm-5250ced83173c9534b4a2723b7a50b67b7c7a6ee.tar.gz
target-microblaze: Set the PC in reset instead of realize
Set the Microblaze CPU PC in the reset instead of setting it in the realize. This is required as the PC is zeroed in the reset function and causes problems in some situations. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-microblaze/cpu.c')
-rw-r--r--target-microblaze/cpu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 9ac509af3e..cbd84a22f7 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -107,6 +107,8 @@ static void mb_cpu_reset(CPUState *s)
/* Disable stack protector. */
env->shr = ~0;
+ env->sregs[SR_PC] = cpu->cfg.base_vectors;
+
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
@@ -183,8 +185,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
- env->sregs[SR_PC] = cpu->cfg.base_vectors;
-
mcc->parent_realize(dev, errp);
}