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authorRichard Henderson <rth@twiddle.net>2015-08-14 07:59:22 -0700
committerLaurent Vivier <laurent@vivier.eu>2016-10-25 20:54:47 +0200
commitb459e3eccfae7fe83e30187c391de00bccf4f51d (patch)
tree0e95d43fa49b1029ae5bcc9892664b4548056bab /target-m68k
parent6a432295d73df91890dc70c4a94dcc4ba88ad1c3 (diff)
downloadqemu-arm-b459e3eccfae7fe83e30187c391de00bccf4f51d.tar.gz
target-m68k: Use setcond for scc
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target-m68k')
-rw-r--r--target-m68k/translate.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 4a650e1f0e..5cc5e14bb6 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -865,19 +865,21 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
DISAS_INSN(scc)
{
- TCGLabel *l1;
+ DisasCompare c;
int cond;
- TCGv reg;
+ TCGv reg, tmp;
- l1 = gen_new_label();
cond = (insn >> 8) & 0xf;
+ gen_cc_cond(&c, s, cond);
+
+ tmp = tcg_temp_new();
+ tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
+ free_cond(&c);
+
reg = DREG(insn, 0);
- tcg_gen_andi_i32(reg, reg, 0xffffff00);
- /* This is safe because we modify the reg directly, with no other values
- live. */
- gen_jmpcc(s, cond ^ 1, l1);
- tcg_gen_ori_i32(reg, reg, 0xff);
- gen_set_label(l1);
+ tcg_gen_neg_i32(tmp, tmp);
+ tcg_gen_deposit_i32(reg, reg, tmp, 0, 8);
+ tcg_temp_free(tmp);
}
/* Force a TB lookup after an instruction that changes the CPU state. */