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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-30 16:25:37 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-30 16:25:37 +0000
commit1addc7c5a11e9fe1811c792614516ed12689a1f0 (patch)
treed78d7ea7a7b17f7af53f6d598c7a89db9296a306 /target-m68k/translate.c
parentd92620c8e0fd51847db7d980e7dbd411e905e822 (diff)
downloadqemu-arm-1addc7c5a11e9fe1811c792614516ed12689a1f0.tar.gz
Spelling and grammar fixes
Minor fixes of spelling and grammar in comments and documentation Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5835 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-m68k/translate.c')
-rw-r--r--target-m68k/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 5c27a7e6bb..bc2fe2b619 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -503,7 +503,7 @@ static inline TCGv gen_extend(TCGv val, int opsize, int sign)
}
/* Generate code for an "effective address". Does not adjust the base
- register for autoincrememnt addressing modes. */
+ register for autoincrement addressing modes. */
static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
{
TCGv reg;