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authorAndreas Färber <afaerber@suse.de>2013-06-21 20:20:45 +0200
committerAndreas Färber <afaerber@suse.de>2013-07-23 02:41:32 +0200
commited2803da58355413447f8c7c681a76873168114f (patch)
tree3772ea93bce05d67ccbd4194eb77173dc46a5706 /target-lm32
parent801c4c287b7d85fe8447900f78a9a6ab89d00271 (diff)
downloadqemu-arm-ed2803da58355413447f8c7c681a76873168114f.tar.gz
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-lm32')
-rw-r--r--target-lm32/translate.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index ed12f50740..1247287050 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1015,6 +1015,7 @@ static inline
void gen_intermediate_code_internal(LM32CPU *cpu,
TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
CPULM32State *env = &cpu->env;
struct DisasContext ctx, *dc = &ctx;
uint16_t *gen_opc_end;
@@ -1032,7 +1033,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->nr_nops = 0;
if (pc_start & 3) {
@@ -1077,7 +1078,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
} while (!dc->is_jmp
&& tcg_ctx.gen_opc_ptr < gen_opc_end
- && !env->singlestep_enabled
+ && !cs->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
@@ -1086,7 +1087,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
gen_io_end();
}
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(cs->singlestep_enabled)) {
if (dc->is_jmp == DISAS_NEXT) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
}