aboutsummaryrefslogtreecommitdiff
path: root/target-lm32
diff options
context:
space:
mode:
authorAndreas Färber <afaerber@suse.de>2013-06-28 23:18:47 +0200
committerAndreas Färber <afaerber@suse.de>2013-07-26 23:23:54 +0200
commita0e372f0c49ac01faeaeb73a6e8f50e8ac615f34 (patch)
tree0a87f5f9ab3ff51ef996c69ded7cfa8f97768e92 /target-lm32
parent19a77215f1ba966c4d37dadec45f38be789b8529 (diff)
downloadqemu-arm-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.gz
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-lm32')
-rw-r--r--target-lm32/cpu.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index ce55e4807d..aa52696cda 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -91,6 +91,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
#endif
+ cc->gdb_num_core_regs = 32 + 7;
}
static const TypeInfo lm32_cpu_type_info = {