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authorRichard Henderson <rth@twiddle.net>2016-03-01 08:59:32 -0800
committerRichard Henderson <rth@twiddle.net>2016-03-14 10:52:42 -0700
commita657f79e32422634415c09f3f15c73d610297af5 (patch)
tree4faccbb8e9f3433bb5dbd750fbfcb8c1e268280e /target-i386/translate.c
parent880f8486503b32a29b653a3c0b3cfc5432012f38 (diff)
downloadqemu-arm-a657f79e32422634415c09f3f15c73d610297af5.tar.gz
target-i386: Fix SMSW for 64-bit mode
In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/translate.c')
-rw-r--r--target-i386/translate.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 10cc2fa8e5..b73c237c9e 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7282,12 +7282,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
CASE_MODRM_OP(4): /* smsw */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
-#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
- tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]) + 4);
-#else
- tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]));
-#endif
- gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1);
+ tcg_gen_ld_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]));
+ if (CODE64(s)) {
+ mod = (modrm >> 6) & 3;
+ ot = (mod != 3 ? MO_16 : s->dflag);
+ } else {
+ ot = MO_16;
+ }
+ gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
CASE_MODRM_OP(6): /* lmsw */