diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2012-10-12 15:04:10 +0200 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-02-18 15:03:57 -0800 |
| commit | 3b9d3cf1609ec98411508c1e8b6dde711117825f (patch) | |
| tree | 0736933250b3a78202097044f6fb8dc69a9a17fc /target-i386/translate.c | |
| parent | 57eb0cc85469a8948d1036ab830951e63aa32f66 (diff) | |
target-i386: kill cpu_T3
It is almost unused, and it is simpler to pass a TCG value directly
to gen_shiftd_rm_T1_T3. This value is then written to t2 without
going through a temporary register.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/translate.c')
| -rw-r--r-- | target-i386/translate.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 9d5467dbfb..60c1fdd29a 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -64,7 +64,7 @@ static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst; static TCGv_i32 cpu_cc_op; static TCGv cpu_regs[CPU_NB_REGS]; /* local temps */ -static TCGv cpu_T[2], cpu_T3; +static TCGv cpu_T[2]; /* local register indexes (only used inside old micro ops) */ static TCGv cpu_tmp0, cpu_tmp4; static TCGv_ptr cpu_ptr0, cpu_ptr1; @@ -1858,8 +1858,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, } /* XXX: add faster immediate case */ -static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, - int is_right) +static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1, + int is_right, TCGv count) { int label1, label2, data_bits; target_ulong mask; @@ -1883,10 +1883,8 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, gen_op_mov_v_reg(ot, t0, op1); } - tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); - + tcg_gen_andi_tl(t2, count, mask); tcg_gen_mov_tl(t1, cpu_T[1]); - tcg_gen_mov_tl(t2, cpu_T3); /* Must test zero case to avoid using undefined behaviour in TCG shifts. */ @@ -5583,12 +5581,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_mov_TN_reg(ot, 1, reg); if (shift) { - val = cpu_ldub_code(env, s->pc++); - tcg_gen_movi_tl(cpu_T3, val); + TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++)); + gen_shiftd_rm_T1(s, ot, opreg, op, imm); + tcg_temp_free(imm); } else { - tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); + gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); } - gen_shiftd_rm_T1_T3(s, ot, opreg, op); break; /************************/ @@ -7869,7 +7867,6 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, cpu_T[0] = tcg_temp_new(); cpu_T[1] = tcg_temp_new(); cpu_A0 = tcg_temp_new(); - cpu_T3 = tcg_temp_new(); cpu_tmp0 = tcg_temp_new(); cpu_tmp1_i64 = tcg_temp_new_i64(); |