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authorAndre Przywara <andre.przywara@amd.com>2009-09-19 00:30:48 +0200
committerAurelien Jarno <aurelien@aurel32.net>2009-10-04 14:09:41 +0200
commitd9f4bb27dbff2e40ec2e36eb8017c9dedce77f30 (patch)
tree60e4374cd0a5fd95cfadb397f0413468d11a1f14 /target-i386/ops_sse_header.h
parentccd59d09a9d0c75b86185b89d8246e40b5f01168 (diff)
target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386/ops_sse_header.h')
-rw-r--r--target-i386/ops_sse_header.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-i386/ops_sse_header.h b/target-i386/ops_sse_header.h
index 53add99f99..a0a63613a1 100644
--- a/target-i386/ops_sse_header.h
+++ b/target-i386/ops_sse_header.h
@@ -187,6 +187,10 @@ DEF_HELPER_2(rsqrtps, void, XMMReg, XMMReg)
DEF_HELPER_2(rsqrtss, void, XMMReg, XMMReg)
DEF_HELPER_2(rcpps, void, XMMReg, XMMReg)
DEF_HELPER_2(rcpss, void, XMMReg, XMMReg)
+DEF_HELPER_2(extrq_r, void, XMMReg, XMMReg)
+DEF_HELPER_3(extrq_i, void, XMMReg, int, int)
+DEF_HELPER_2(insertq_r, void, XMMReg, XMMReg)
+DEF_HELPER_3(insertq_i, void, XMMReg, int, int)
DEF_HELPER_2(haddps, void, XMMReg, XMMReg)
DEF_HELPER_2(haddpd, void, XMMReg, XMMReg)
DEF_HELPER_2(hsubps, void, XMMReg, XMMReg)