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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2015-10-27 12:00:50 +0000
committerPeter Maydell <peter.maydell@linaro.org>2015-10-27 12:00:50 +0000
commitb876452507d0b719cff0b478efafb34ac41db683 (patch)
tree8dd25232262f35d9d92acd76c35fa1c86b395407 /target-arm
parent541ebcd401ee47f3c1a3ce503ef5466b75e9d20a (diff)
downloadqemu-arm-b876452507d0b719cff0b478efafb34ac41db683.tar.gz
target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/helper.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e7fda37466..aba5025403 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3288,6 +3288,22 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.type = ARM_CP_ALIAS,
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
+ { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[4]) },
+ { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[2]) },
+ { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[3]) },
+ { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[5]) },
{ .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
.access = PL2_RW, .writefn = vbar_write,