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authorPeter Maydell <peter.maydell@linaro.org>2016-01-21 14:15:06 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-01-21 14:15:06 +0000
commit9e273ef2174d7cd5b14a16d8638812541d3eb6bb (patch)
tree9a2983fde691ef7966aa236f3ab4ff54b8c0e2d8 /target-arm
parent6731d864f80938e404dc3e5eb7f6b76b891e3e43 (diff)
downloadqemu-arm-9e273ef2174d7cd5b14a16d8638812541d3eb6bb.tar.gz
target-arm: Add QOM property for Secure memory region
Add QOM property to the ARM CPU which boards can use to tell us what memory region to use for secure accesses. Nonsecure accesses go via the memory region specified with the base CPU class 'memory' property. By default, if no secure region is specified it is the same as the nonsecure region, and if no nonsecure region is specified we will use address_space_memory. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/cpu-qom.h3
-rw-r--r--target-arm/cpu.c32
-rw-r--r--target-arm/cpu.h6
3 files changed, 41 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 5bd9b7bb9f..333af589bc 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -87,6 +87,9 @@ typedef struct ARMCPU {
/* GPIO outputs for generic timer */
qemu_irq gt_timer_outputs[NUM_GTIMERS];
+ /* MemoryRegion to use for secure physical accesses */
+ MemoryRegion *secure_memory;
+
/* 'compatible' string for this CPU for Linux device trees */
const char *dtb_compatible;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 3f5f8e8cb5..57f1754cbf 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -543,6 +543,15 @@ static void arm_cpu_post_init(Object *obj)
*/
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
&error_abort);
+
+#ifndef CONFIG_USER_ONLY
+ object_property_add_link(obj, "secure-memory",
+ TYPE_MEMORY_REGION,
+ (Object **)&cpu->secure_memory,
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
+ &error_abort);
+#endif
}
if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
@@ -666,6 +675,29 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
init_cpreg_list(cpu);
+#ifndef CONFIG_USER_ONLY
+ if (cpu->has_el3) {
+ cs->num_ases = 2;
+ } else {
+ cs->num_ases = 1;
+ }
+
+ if (cpu->has_el3) {
+ AddressSpace *as;
+
+ if (!cpu->secure_memory) {
+ cpu->secure_memory = cs->memory;
+ }
+ as = address_space_init_shareable(cpu->secure_memory,
+ "cpu-secure-memory");
+ cpu_address_space_init(cs, as, ARMASIdx_S);
+ }
+ cpu_address_space_init(cs,
+ address_space_init_shareable(cs->memory,
+ "cpu-memory"),
+ ARMASIdx_NS);
+#endif
+
qemu_init_vcpu(cs);
cpu_reset(cs);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 815fef8a30..9108b5bd6d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1720,6 +1720,12 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
return el;
}
+/* Indexes used when registering address spaces with cpu_address_space_init */
+typedef enum ARMASIdx {
+ ARMASIdx_NS = 0,
+ ARMASIdx_S = 1,
+} ARMASIdx;
+
/* Return the Exception Level targeted by debug exceptions;
* currently always EL1 since we don't implement EL2 or EL3.
*/