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authorSergey Sorokin <afarallax@yandex.ru>2015-10-16 11:14:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-10-16 11:14:52 +0100
commit2cde031f5a34996bab32571a26b1a6bcf3e5b5d9 (patch)
tree8ac0b45996a034a6de7e20376d16ddc1e0212dc7 /target-arm
parent6df99dec9e81838423d723996e96236693fa31fe (diff)
downloadqemu-arm-2cde031f5a34996bab32571a26b1a6bcf3e5b5d9.tar.gz
target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL
It is incorrect to call arm_el_is_aa64() function for unimplemented EL. This patch fixes several attempts to do so. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> [PMM: Reworked several of the comments to be more verbose.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/cpu.h11
-rw-r--r--target-arm/helper.c15
2 files changed, 21 insertions, 5 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 493f9d02a9..5fb0479b2a 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1016,11 +1016,11 @@ static inline bool access_secure_reg(CPUARMState *env)
*/
#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
A32_BANKED_REG_GET((_env), _regname, \
- ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))))
+ (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
A32_BANKED_REG_SET((_env), _regname, \
- ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \
+ (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
(_val))
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
@@ -1587,7 +1587,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
* interrupt.
*/
if ((target_el > cur_el) && (target_el != 1)) {
- if (arm_el_is_aa64(env, 3) || ((scr || hcr) && (!secure))) {
+ /* ARM_FEATURE_AARCH64 enabled means the highest EL is AArch64.
+ * This code currently assumes that EL2 is not implemented
+ * (and so that highest EL will be 3 and the target_el also 3).
+ */
+ if (arm_feature(env, ARM_FEATURE_AARCH64) ||
+ ((scr || hcr) && (!secure))) {
unmasked = 1;
}
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b4986705c4..b2d78b0192 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5224,11 +5224,22 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure)
{
CPUARMState *env = cs->env_ptr;
- int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
+ int rw;
int scr;
int hcr;
int target_el;
- int is64 = arm_el_is_aa64(env, 3);
+ /* Is the highest EL AArch64? */
+ int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
+
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
+ } else {
+ /* Either EL2 is the highest EL (and so the EL2 register width
+ * is given by is64); or there is no EL2 or EL3, in which case
+ * the value of 'rw' does not affect the table lookup anyway.
+ */
+ rw = is64;
+ }
switch (excp_idx) {
case EXCP_IRQ: