aboutsummaryrefslogtreecommitdiff
path: root/target-arm
diff options
context:
space:
mode:
authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2015-10-26 14:01:56 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-10-27 15:59:46 +0000
commit1f4c8c18a5b6f4fad13e13b7e3828124c6c8f34d (patch)
treee194d6beafedb091fb3548b8eb7d06589369eee6 /target-arm
parent5c31a10d16c595d6a59e3e7fc1808c3b1d03e02f (diff)
downloadqemu-arm-1f4c8c18a5b6f4fad13e13b7e3828124c6c8f34d.tar.gz
target-arm: lpae: Move declaration of t0sz and t1sz
Move declaration of t0sz and t1sz to the top of the function avoiding a mix of code and variable declarations. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/helper.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d07b4b7cf3..0086febf43 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6480,6 +6480,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
MMUFaultType fault_type = translation_fault;
uint32_t level = 1;
uint32_t epd = 0;
+ int32_t t0sz, t1sz;
int32_t tsz;
uint32_t tg;
uint64_t ttbr;
@@ -6535,12 +6536,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
*/
- int32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
+ t0sz = extract32(tcr->raw_tcr, 0, 6);
if (va_size == 64) {
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
}
- int32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
+ t1sz = extract32(tcr->raw_tcr, 16, 6);
if (va_size == 64) {
t1sz = MIN(t1sz, 39);
t1sz = MAX(t1sz, 16);