path: root/target-arm/translate.c
diff options
authorPeter Maydell <peter.maydell@linaro.org>2016-02-11 11:17:31 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-02-11 11:17:31 +0000
commit3f208fd76bcc91a8506681bb8472f2398fe6f487 (patch)
treebc3d1894f35937be8e3c75a77e79d687fa7d8c21 /target-arm/translate.c
parent533e93f1cf12c570aab45f14663dab6fb8ea3ffc (diff)
target-arm: Add isread parameter to CPAccessFns
System registers might have access requirements which need to be described via a CPAccessFn and which differ for reads and writes. For this to be possible we need to pass the access function a parameter to tell it whether the access being checked is a read or a write. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-6-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate.c')
1 files changed, 5 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f6a38bcc09..2c8213b07a 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7169,7 +7169,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
* call in order to handle c15_cpar.
TCGv_ptr tmpptr;
- TCGv_i32 tcg_syn;
+ TCGv_i32 tcg_syn, tcg_isread;
uint32_t syndrome;
/* Note that since we are an implementation which takes an
@@ -7214,9 +7214,12 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
gen_set_pc_im(s, s->pc - 4);
tmpptr = tcg_const_ptr(ri);
tcg_syn = tcg_const_i32(syndrome);
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn);
+ tcg_isread = tcg_const_i32(isread);
+ gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn,
+ tcg_isread);
+ tcg_temp_free_i32(tcg_isread);
/* Handle special cases first */