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authorPeter Maydell <peter.maydell@linaro.org>2014-10-28 19:24:04 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-11-04 12:05:11 +0000
commitf4df22102a0081ff1bd0df4cb5552411e410eb3e (patch)
tree196ea2f603a5e7fe9f5f2f8bbe4fe89c69ba2c03 /target-arm/translate.c
parent7dcc1f894d6c50b4f20ce3d2e9c1a90165bc85af (diff)
downloadqemu-arm-f4df22102a0081ff1bd0df4cb5552411e410eb3e.tar.gz
target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()
Refactor to avoid passing a CPUARMState * to disas_arm_insn(). To do this we move the "read insn from memory" code to the callsite and pass the insn to the function instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1414524244-20316-6-git-send-email-peter.maydell@linaro.org Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c9c6d911ba..af5156857e 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7560,18 +7560,15 @@ static void gen_srs(DisasContext *s,
tcg_temp_free_i32(addr);
}
-static void disas_arm_insn(CPUARMState * env, DisasContext *s)
+static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
+ unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
TCGv_i32 tmp;
TCGv_i32 tmp2;
TCGv_i32 tmp3;
TCGv_i32 addr;
TCGv_i64 tmp64;
- insn = arm_ldl_code(env, s->pc, s->bswap_code);
- s->pc += 4;
-
/* M variants do not implement ARM mode. */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
goto illegal_op;
@@ -11199,7 +11196,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
}
}
} else {
- disas_arm_insn(env, dc);
+ unsigned int insn = arm_ldl_code(env, dc->pc, dc->bswap_code);
+ dc->pc += 4;
+ disas_arm_insn(dc, insn);
}
if (dc->condjmp && !dc->is_jmp) {