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authorPeter Maydell <peter.maydell@linaro.org>2014-03-17 16:31:47 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-03-17 16:31:47 +0000
commita984e42c916ad5afdf3f8660f284857547943aa4 (patch)
treecd3e835f0f03c47c328bb5a4e03a8b082a9306de /target-arm/translate.c
parentd6d60581f3f6778de85ee23427006151b5226667 (diff)
downloadqemu-arm-a984e42c916ad5afdf3f8660f284857547943aa4.tar.gz
target-arm: A64: Implement PMULL instruction
Implement the PMULL instruction; this is the last unimplemented insn in the three-reg-diff group. Note that PMULL with size 3 is considered part of the AES part of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition in the v8 ARM ARM), so it isn't necessary to burn an extra feature bit on it, even though we're using more feature bits than a single "crypto extension present/not present" toggle. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index fbe513b40d..20042976f2 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -10654,6 +10654,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
dc->cp_regs = cpu->cp_regs;
dc->current_pl = arm_current_pl(env);
+ dc->features = env->features;
cpu_F0s = tcg_temp_new_i32();
cpu_F1s = tcg_temp_new_i32();