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authorPeter Maydell <peter.maydell@linaro.org>2014-04-15 19:18:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-04-17 21:34:04 +0100
commita50c0f51339ed1df0a2e289513e3e2bf5b5ca45c (patch)
tree21ccde90de2f8ff2c25e6c3fd617da9233b9ca88 /target-arm/translate.c
parent52e60cdd342dc48116edb81b443ba8c0a0c6f1a3 (diff)
downloadqemu-arm-a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c.tar.gz
target-arm: Implement ARMv8 MVFR registers
For ARMv8 there are two changes to the MVFR media feature registers: * there is a new MVFR2 which is accessible from 32 bit code * 64 bit code accesses these via the usual sysreg instructions rather than with a floating-point specific instruction Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 03e2c00e94..f7b5dafcb7 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2967,9 +2967,10 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
if ((insn & 0x0fe00fff) != 0x0ee00a10)
return 1;
rn = (insn >> 16) & 0xf;
- if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
- && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
+ if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC && rn != ARM_VFP_MVFR2
+ && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) {
return 1;
+ }
}
if (extract32(insn, 28, 4) == 0xf) {
@@ -3115,6 +3116,11 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
gen_helper_vfp_get_fpscr(tmp, cpu_env);
}
break;
+ case ARM_VFP_MVFR2:
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
+ return 1;
+ }
+ /* fall through */
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
if (IS_USER(s)