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authorPeter Maydell <peter.maydell@linaro.org>2014-10-24 12:19:14 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-10-24 12:19:14 +0100
commit23adb8618caf24ab7cbb41fb2f27bad1c429cbda (patch)
treef4cac950e22e7d629ec7c7b07ff93dfa41777fd2 /target-arm/translate.c
parent0e7b176ae01d5a664d4cbf619a7315819494e6cb (diff)
downloadqemu-arm-23adb8618caf24ab7cbb41fb2f27bad1c429cbda.tar.gz
target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0
The ARM ARM requires that the FPINST and FPINST2 VFP control registers are not accessible to code at EL0. We were already correctly implementing this for reads of these registers; add the missing check for the write code path. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1412967447-20931-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4e764d340b..656b09e115 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -3232,6 +3232,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
break;
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
+ if (IS_USER(s)) {
+ return 1;
+ }
tmp = load_reg(s, rd);
store_cpu_field(tmp, vfp.xregs[rn]);
break;