diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2016-03-04 11:30:20 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-03-04 11:30:20 +0000 |
| commit | dacf0a2ff7d39ab12bd90f2f5496a3889facd54a (patch) | |
| tree | ff37020225b860825099eacafb98aa99aa054bc0 /target-arm/translate-a64.c | |
| parent | 12dcc3217dc86b7dccee293b2f6e3fa4f7b014ae (diff) | |
target-arm: introduce disas flag for endianness
Introduce a disas flag for setting the CPU data endianness. This allows
control of the endianness from the CPU state rather than hard-coding it
to TARGET_WORDS_BIGENDIAN.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[ PC changes:
* Split off as new patch from original:
"target-arm: introduce tbflag for CPSR.E"
* Wrote commit message from scratch
]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index f6dd44b86f..88b95ab138 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11032,6 +11032,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; + dc->be_data = MO_TE; dc->condexec_mask = 0; dc->condexec_cond = 0; dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags); |