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authorRob Herring <rob.herring@linaro.org>2014-04-15 19:18:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-04-17 21:34:04 +0100
commit52e60cdd342dc48116edb81b443ba8c0a0c6f1a3 (patch)
tree03c2b84affc505cae383fdd0782a5d06539a1118 /target-arm/cpu64.c
parent2f2a00aec9838bc52ac4f5dd452f4cf533effa88 (diff)
target-arm: Implement AArch64 EL1 exception handling
Implement exception handling for AArch64 EL1. Exceptions from AArch64 or AArch32 EL0 are supported. Signed-off-by: Rob Herring <rob.herring@linaro.org> [PMM: fixed minor style nits; updated to match changes in previous patches; added some of the simpler cases of illegal-exception-return support] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu64.c')
-rw-r--r--target-arm/cpu64.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index fccecc2527..d4fb1de4fa 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -85,6 +85,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
+ cc->do_interrupt = aarch64_cpu_do_interrupt;
cc->dump_state = aarch64_cpu_dump_state;
cc->set_pc = aarch64_cpu_set_pc;
cc->gdb_read_register = aarch64_cpu_gdb_read_register;