path: root/target-arm/cpu64.c
diff options
authorAlexander Graf <agraf@suse.de>2013-09-03 20:12:10 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-09-10 19:11:28 +0100
commit14ade10f840deec02d32530e5a64bd5ec275adbd (patch)
treef44cafcc01b2e7846c824d0a8f1476ff019ddb5f /target-arm/cpu64.c
parent3926cc8433542e8c9b7cdc438355fb7660838fd0 (diff)
target-arm: Add AArch64 translation stub
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode, registers look vastly different, instruction encoding is completely different, basically the system turns into a different machine. So let's do a simple if() in translate.c to decide whether we can handle the current code in the legacy AArch32 code or in the new AArch64 code. So far, the translation always complains about unallocated instructions. There is no emulator functionality in this patch! Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org [PMM: * provide no-op versions of a64 functions ifndef TARGET_AARCH64; this lets us avoid #ifdefs in translate.c * insert the missing call to disas_a64_insn() * stash the insn in the DisasContext rather than reloading it in real_unallocated_encoding() ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu64.c')
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index faee0f048f..4428f6cffd 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -70,6 +70,9 @@ static void aarch64_cpu_finalizefn(Object *obj)
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
+ CPUClass *cc = CPU_CLASS(oc);
+ cc->dump_state = aarch64_cpu_dump_state;
static void aarch64_cpu_register(const ARMCPUInfo *info)