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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:19 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:09:11 +0000 |
| commit | 8515a092948584ce112b90030edcef344c6a0f90 (patch) | |
| tree | 470a6f467845f018b8bdf70601f7b380b18f7518 /target-arm/cpu.h | |
| parent | 2771db274193420b82f988b995282820631cdd99 (diff) | |
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 02d86ca8aa..095354304a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -111,8 +111,6 @@ typedef struct CPUARMState { uint32_t c0_ccsid[16]; /* Cache size. */ uint32_t c0_clid; /* Cache level. */ uint32_t c0_cssel; /* Cache size selection. */ - uint32_t c0_c1[8]; /* Feature registers. */ - uint32_t c0_c2[8]; /* Instruction set registers. */ uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |