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authorPeter Maydell <peter.maydell@linaro.org>2013-09-10 19:09:32 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-09-10 19:09:32 +0100
commit78dbbbe4dff95369c63bf77ee0df23371e1d6602 (patch)
treee313eb5118e9f02d616b0a6a286c0722d48a23da /target-arm/cpu.h
parent534df156090539854c2ac819dcdb096d01dab5c1 (diff)
target-arm: Avoid "1 << 31" undefined behaviour
Avoid the undefined behaviour of "1 << 31" by using 1U to make the shift be of an unsigned value rather than shifting into the sign bit of a signed integer. For consistency, we make all the CPSR_* constants unsigned, though the only one which triggers undefined behaviour is CPSR_N. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h32
1 files changed, 16 insertions, 16 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f2abdf37ce..af7cf8ac51 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -270,22 +270,22 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
-#define CPSR_M (0x1f)
-#define CPSR_T (1 << 5)
-#define CPSR_F (1 << 6)
-#define CPSR_I (1 << 7)
-#define CPSR_A (1 << 8)
-#define CPSR_E (1 << 9)
-#define CPSR_IT_2_7 (0xfc00)
-#define CPSR_GE (0xf << 16)
-#define CPSR_RESERVED (0xf << 20)
-#define CPSR_J (1 << 24)
-#define CPSR_IT_0_1 (3 << 25)
-#define CPSR_Q (1 << 27)
-#define CPSR_V (1 << 28)
-#define CPSR_C (1 << 29)
-#define CPSR_Z (1 << 30)
-#define CPSR_N (1 << 31)
+#define CPSR_M (0x1fU)
+#define CPSR_T (1U << 5)
+#define CPSR_F (1U << 6)
+#define CPSR_I (1U << 7)
+#define CPSR_A (1U << 8)
+#define CPSR_E (1U << 9)
+#define CPSR_IT_2_7 (0xfc00U)
+#define CPSR_GE (0xfU << 16)
+#define CPSR_RESERVED (0xfU << 20)
+#define CPSR_J (1U << 24)
+#define CPSR_IT_0_1 (3U << 25)
+#define CPSR_Q (1U << 27)
+#define CPSR_V (1U << 28)
+#define CPSR_C (1U << 29)
+#define CPSR_Z (1U << 30)
+#define CPSR_N (1U << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)