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authorPeter Maydell <peter.maydell@linaro.org>2014-02-26 17:20:05 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-02-26 17:20:05 +0000
commite60cef860f76cd558ee70e1d145eea1c24de20e7 (patch)
tree2c8f31f19db06b82dc26bc6a1cf17f461ff6e5a1 /target-arm/cpu-qom.h
parenta7adc4b779d24e75d05d43fb6311ab9e6449523a (diff)
downloadqemu-arm-e60cef860f76cd558ee70e1d145eea1c24de20e7.tar.gz
target-arm: Implement AArch64 ID and feature registers
Implement the AArch64-specific ID and feature registers. Although many of these are currently not used by the architecture (and so always zero for all implementations), we define the full set of fields in the ARMCPU struct for symmetry. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index afbd4222c5..00234e1d3d 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -132,6 +132,16 @@ typedef struct ARMCPU {
uint32_t id_isar3;
uint32_t id_isar4;
uint32_t id_isar5;
+ uint64_t id_aa64pfr0;
+ uint64_t id_aa64pfr1;
+ uint64_t id_aa64dfr0;
+ uint64_t id_aa64dfr1;
+ uint64_t id_aa64afr0;
+ uint64_t id_aa64afr1;
+ uint64_t id_aa64isar0;
+ uint64_t id_aa64isar1;
+ uint64_t id_aa64mmfr0;
+ uint64_t id_aa64mmfr1;
uint32_t clidr;
/* The elements of this array are the CCSIDR values for each cache,
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.