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authorPeter Maydell <peter.maydell@linaro.org>2014-04-15 19:18:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-04-17 21:34:04 +0100
commita50c0f51339ed1df0a2e289513e3e2bf5b5ca45c (patch)
tree21ccde90de2f8ff2c25e6c3fd617da9233b9ca88 /target-arm/cpu-qom.h
parent52e60cdd342dc48116edb81b443ba8c0a0c6f1a3 (diff)
downloadqemu-arm-a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c.tar.gz
target-arm: Implement ARMv8 MVFR registers
For ARMv8 there are two changes to the MVFR media feature registers: * there is a new MVFR2 which is accessible from 32 bit code * 64 bit code accesses these via the usual sysreg instructions rather than with a floating-point specific instruction Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index afdee9d683..2b6b3708f8 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -116,6 +116,7 @@ typedef struct ARMCPU {
uint32_t reset_fpsid;
uint32_t mvfr0;
uint32_t mvfr1;
+ uint32_t mvfr2;
uint32_t ctr;
uint32_t reset_sctlr;
uint32_t id_pfr0;