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authorPeter Maydell <peter.maydell@linaro.org>2012-04-20 17:58:35 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-04-21 18:12:29 +0000
commit85df3786b21191d49d17dcb77f45ae75f6addad0 (patch)
treee075ad99853625aa15939dc554427d713479945d /target-arm/cpu-qom.h
parent8092d2f031e70eb2664d5fa1d9ed00ef1113ee71 (diff)
downloadqemu-arm-85df3786b21191d49d17dcb77f45ae75f6addad0.tar.gz
target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 7603eff604..b6c044a251 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -89,6 +89,11 @@ typedef struct ARMCPU {
uint32_t id_isar3;
uint32_t id_isar4;
uint32_t id_isar5;
+ uint32_t clidr;
+ /* The elements of this array are the CCSIDR values for each cache,
+ * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
+ */
+ uint32_t ccsidr[16];
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)