path: root/target-arm/cpu-qom.h
diff options
authorPeter Maydell <peter.maydell@linaro.org>2013-08-20 14:54:31 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-08-20 14:54:31 +0100
commit55d284af8e31bbdf4d545cb2d6481cd0367680fb (patch)
tree954a9624cca40d7c9bbbd7604f45201472b6a50a /target-arm/cpu-qom.h
parent2452731c883cb0acd4e47b23039c46cd880cf2c6 (diff)
target-arm: Implement the generic timer
The ARMv7 architecture specifies a 'generic timer' which is implemented via cp15 registers. Newer kernels will prefer to use this rather than a devboard-level timer. Implement the generic timer for TCG; for KVM we will already use the hardware's virtualized timer for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1376065080-26661-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu-qom.h')
1 files changed, 9 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index cf3658714e..9f47baebf8 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -86,6 +86,11 @@ typedef struct ARMCPU {
uint64_t *cpreg_vmstate_values;
int32_t cpreg_vmstate_array_len;
+ /* Timers used by the generic (architected) timer */
+ QEMUTimer *gt_timer[NUM_GTIMERS];
+ /* GPIO outputs for generic timer */
+ qemu_irq gt_timer_outputs[NUM_GTIMERS];
/* The instance init functions for implementation-specific subclasses
* set these fields to specify the implementation-dependent values of
* various constant registers and reset values of non-constant
@@ -152,4 +157,8 @@ hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+/* Callback functions for the generic timer's timers. */
+void arm_gt_ptimer_cb(void *opaque);
+void arm_gt_vtimer_cb(void *opaque);