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authorPeter Maydell <peter.maydell@linaro.org>2014-08-19 18:56:25 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-08-19 19:02:03 +0100
commit48eb3ae64b3e17151cf8f42af185e6f43baf707b (patch)
tree99dd56aaba44dbdc92537de9e76c5f07a5946b21 /target-arm/cpu-qom.h
parent10aae1049fe90b84798af2751051ea896437a831 (diff)
downloadqemu-arm-48eb3ae64b3e17151cf8f42af185e6f43baf707b.tar.gz
target-arm: Adjust debug ID registers per-CPU
Allow each CPU type to specify the value for the debug ID registers, by putting them in the ARMCPU struct, and use the resulting information to only expose the correct number of watchpoint and breakpoint registers for the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index ee4fbb1dad..07f3c9e866 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -148,6 +148,7 @@ typedef struct ARMCPU {
uint64_t id_aa64isar1;
uint64_t id_aa64mmfr0;
uint64_t id_aa64mmfr1;
+ uint32_t dbgdidr;
uint32_t clidr;
/* The elements of this array are the CCSIDR values for each cache,
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.