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authorPeter Maydell <peter.maydell@linaro.org>2014-04-15 19:18:48 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-04-17 21:34:06 +0100
commit3933443e38f37576d63247a846ca342da53e7d43 (patch)
tree5dec05752805f6af715c8ff296cac458831c28c1 /target-arm/cpu-qom.h
parent19525524a755a98f72b80c92c4f6bdeea3002da5 (diff)
downloadqemu-arm-3933443e38f37576d63247a846ca342da53e7d43.tar.gz
target-arm: Implement RVBAR register
Implement the AArch64 RVBAR register, which indicates the reset address. Since the reset address is implementation defined and usually configurable by setting config signals in hardware, we also provide a QOM property so it can be set at board level if necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 2b6b3708f8..743985ec2d 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -153,6 +153,7 @@ typedef struct ARMCPU {
bool reset_hivecs;
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
uint32_t dcz_blocksize;
+ uint64_t rvbar;
} ARMCPU;
#define TYPE_AARCH64_CPU "aarch64-cpu"