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authorPeter Maydell <peter.maydell@linaro.org>2016-02-19 14:07:43 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-02-26 15:09:42 +0000
commite20d84c1407d43d5a2e2ac95dbb46db3b0af8f9f (patch)
tree820337c9a61aecda51fd87f6c98eee41247aa235 /target-arm/cpu-qom.h
parentd44ec156300a149b386a14d3ab349d3b83b66b8c (diff)
downloadqemu-arm-e20d84c1407d43d5a2e2ac95dbb46db3b0af8f9f.tar.gz
target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFpull-target-arm-20160226
The v8 ARM ARM defines that unused spaces in the ID_AA64* system register ranges are Reserved and must RAZ, rather than being UNDEF. Implement this. In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2, and newer versions of the Linux kernel will attempt to read this, which causes them not to boot up on versions of QEMU missing this fix. Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6 is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in the ARMCPU struct so CPUs can override it, though since none do this too will just RAZ. Cc: qemu-stable@nongnu.org Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455890863-11203-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'target-arm/cpu-qom.h')
-rw-r--r--target-arm/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 1cc4502fc4..1061c08a10 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -155,6 +155,7 @@ typedef struct ARMCPU {
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
+ uint32_t id_mmfr4;
uint32_t id_isar0;
uint32_t id_isar1;
uint32_t id_isar2;