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authorRichard Henderson <rth@twiddle.net>2014-03-19 00:12:43 -0700
committerRichard Henderson <rth@twiddle.net>2014-04-17 11:47:41 -0700
commit8f56ced8aa1a8a2846bc0c4919032101c6e3a2fc (patch)
tree574b4cbb6a02f94a16bb29b47891eccd51652027 /target-alpha
parent89fe090bb39295a15fa47d5bf2d906cf7e0e6474 (diff)
downloadqemu-arm-8f56ced8aa1a8a2846bc0c4919032101c6e3a2fc.tar.gz
target-alpha: Convert opcode 0x1A to source/sink
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-alpha')
-rw-r--r--target-alpha/translate.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 334091637e..d3fbcb433b 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2735,6 +2735,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc;
}
break;
+
case 0x19:
/* HW_MFPR (PALcode) */
#ifndef CONFIG_USER_ONLY
@@ -2743,14 +2744,12 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
#else
goto invalid_opc;
#endif
+
case 0x1A:
/* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch
prediction stack action, which of course we don't implement. */
- if (rb != 31) {
- tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
- } else {
- tcg_gen_movi_i64(cpu_pc, 0);
- }
+ vb = load_gpr(ctx, rb);
+ tcg_gen_andi_i64(cpu_pc, vb, ~3);
if (ra != 31) {
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
}