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authorVince Weaver <vince@csl.cornell.edu>2009-09-17 15:28:52 -0400
committerAurelien Jarno <aurelien@aurel32.net>2009-09-18 17:22:37 +0200
commitdbf95805889fc3d7502e39bbb4c8b7ea5c24fffd (patch)
tree440396b7d15eba72fba0541a3f47e9e2186027c1 /target-alpha
parent7fd6bf7daecebb8be9a6eac6ddba60b502f70f40 (diff)
target-alpha: fix extlh instruction
The extlh instruction on Alpha currently doesn't work properly. It's a combination of a cut/paste bug (16 where it should be 32) as well as a "shift by 64" bug. Signed-off-by: Vince Weaver <vince@csl.cornell.edu> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-alpha')
-rw-r--r--target-alpha/translate.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 9d2bc45d86..9e7e9b2d83 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -524,14 +524,15 @@ static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
else
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
} else {
- TCGv tmp1, tmp2;
+ TCGv tmp1;
tmp1 = tcg_temp_new();
+
tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
tcg_gen_shli_i64(tmp1, tmp1, 3);
- tmp2 = tcg_const_i64(64);
- tcg_gen_sub_i64(tmp1, tmp2, tmp1);
- tcg_temp_free(tmp2);
+ tcg_gen_neg_i64(tmp1, tmp1);
+ tcg_gen_andi_i64(tmp1, tmp1, 0x3f);
tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
+
tcg_temp_free(tmp1);
}
if (tcg_gen_ext_i64)
@@ -1316,7 +1317,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x6A:
/* EXTLH */
- gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
+ gen_ext_h(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
break;
case 0x72:
/* MSKQH */