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authorRichard Henderson <rth@twiddle.net>2014-03-18 23:59:59 -0700
committerRichard Henderson <rth@twiddle.net>2014-04-17 11:47:41 -0700
commit6b88b37c0efb183b0270ac41c57129813731a80f (patch)
treecc11cbfc0e419d55f9950b56ee64924344917aa8 /target-alpha
parent075b8ddb9b27a24b82ca6ba0b9d8421249b86d8d (diff)
target-alpha: Convert opcode 0x17 to source/sink
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-alpha')
-rw-r--r--target-alpha/translate.c41
1 files changed, 20 insertions, 21 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 2afda7791d..e783e80d81 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -197,7 +197,7 @@ static TCGv dest_gpr(DisasContext *ctx, unsigned reg)
}
}
-static TCGv __attribute__((unused)) load_fpr(DisasContext *ctx, unsigned reg)
+static TCGv load_fpr(DisasContext *ctx, unsigned reg)
{
if (likely(reg < 31)) {
return cpu_fir[reg];
@@ -2429,6 +2429,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc;
}
break;
+
case 0x15:
/* VAX floating point */
/* XXX: rounding mode and trap are ignored (!) */
@@ -2509,6 +2510,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc;
}
break;
+
case 0x16:
/* IEEE floating-point */
switch (fpfn) { /* fn11 & 0x3F */
@@ -2589,6 +2591,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc;
}
break;
+
case 0x17:
switch (fn11) {
case 0x010:
@@ -2597,18 +2600,20 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
gen_fcvtlq(rb, rc);
break;
case 0x020:
- if (likely(rc != 31)) {
- if (ra == rb) {
- /* FMOV */
- if (ra == 31) {
- tcg_gen_movi_i64(cpu_fir[rc], 0);
- } else {
- tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);
- }
+ /* CPYS */
+ if (rc == 31) {
+ /* Special case CPYS as FNOP. */
+ } else if (ra == rb) {
+ vc = dest_fpr(ctx, rc);
+ /* Special case CPYS as FMOV. */
+ if (ra == 31) {
+ tcg_gen_movi_i64(vc, 0);
} else {
- /* CPYS */
- gen_fcpys(ra, rb, rc);
+ va = load_fpr(ctx, ra);
+ tcg_gen_mov_i64(vc, va);
}
+ } else {
+ gen_fcpys(ra, rb, rc);
}
break;
case 0x021:
@@ -2621,19 +2626,13 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x024:
/* MT_FPCR */
- if (likely(ra != 31)) {
- gen_helper_store_fpcr(cpu_env, cpu_fir[ra]);
- } else {
- TCGv tmp = tcg_const_i64(0);
- gen_helper_store_fpcr(cpu_env, tmp);
- tcg_temp_free(tmp);
- }
+ va = load_fpr(ctx, ra);
+ gen_helper_store_fpcr(cpu_env, va);
break;
case 0x025:
/* MF_FPCR */
- if (likely(ra != 31)) {
- gen_helper_load_fpcr(cpu_fir[ra], cpu_env);
- }
+ va = dest_fpr(ctx, ra);
+ gen_helper_load_fpcr(va, cpu_env);
break;
case 0x02A:
/* FCMOVEQ */