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authorRichard Henderson <rth@twiddle.net>2012-03-24 09:51:13 -0700
committerBlue Swirl <blauwirbel@gmail.com>2012-03-24 17:07:32 +0000
commitc30827555d5305d42f7b164dc69a381c4882e77a (patch)
tree89c036e373b12e908e81cfe148eafd074109f848 /target-alpha/translate.c
parent69163fbb0c4d7d3c270bd79d14d6ac076143975e (diff)
downloadqemu-arm-c30827555d5305d42f7b164dc69a381c4882e77a.tar.gz
target-alpha: Move memory helpers to mem_helper.c.
This completes the transition away from AREG0. This patch must be last because it requires CONFIG_TCG_PASS_AREG0 set too. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-alpha/translate.c')
-rw-r--r--target-alpha/translate.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index cc87320ca8..dd09ad8bfe 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2867,11 +2867,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
- gen_helper_ldl_l_phys(cpu_ir[ra], addr);
+ gen_helper_ldl_l_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x3:
/* Quadword physical access with lock (hw_ldq_l/p) */
- gen_helper_ldq_l_phys(cpu_ir[ra], addr);
+ gen_helper_ldq_l_phys(cpu_ir[ra], cpu_env, addr);
break;
case 0x4:
/* Longword virtual PTE fetch (hw_ldl/v) */
@@ -3180,11 +3180,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x2:
/* Longword physical access with lock */
- gen_helper_stl_c_phys(val, addr, val);
+ gen_helper_stl_c_phys(val, cpu_env, addr, val);
break;
case 0x3:
/* Quadword physical access with lock */
- gen_helper_stq_c_phys(val, addr, val);
+ gen_helper_stq_c_phys(val, cpu_env, addr, val);
break;
case 0x4:
/* Longword virtual access */
@@ -3420,7 +3420,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
- insn = ldl_code(ctx.pc);
+ insn = cpu_ldl_code(env, ctx.pc);
num_insns++;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {