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authorRichard Henderson <rth@twiddle.net>2011-05-20 13:11:25 -0700
committerRichard Henderson <rth@anchor.twiddle.net>2011-05-31 10:18:05 -0700
commit8417845ee9dbb2881409bac75365099d17d1cc3d (patch)
tree2b853fb08149cfc83cb4a876cbc6b4769e7d3c93 /target-alpha/translate.c
parente52458fe29ac6f2c0edb17c3f78164200cd047b8 (diff)
downloadqemu-arm-8417845ee9dbb2881409bac75365099d17d1cc3d.tar.gz
target-alpha: Cleanup MMU modes.
Don't bother including executive and supervisor modes. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-alpha/translate.c')
-rw-r--r--target-alpha/translate.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 851a045681..2c0b9c2e6f 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1522,8 +1522,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
#ifndef CONFIG_USER_ONLY
if (palcode < 0x40) {
/* Privileged PAL code */
- if (ctx->mem_idx & 1)
+ if (ctx->mem_idx != MMU_KERNEL_IDX) {
goto invalid_opc;
+ }
ret = gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0);
}
#endif
@@ -2651,11 +2652,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc;
case 0xA:
/* Longword virtual access with protection check (hw_ldl/w) */
- tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
+ tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_KERNEL_IDX);
break;
case 0xB:
/* Quadword virtual access with protection check (hw_ldq/w) */
- tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
+ tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_KERNEL_IDX);
break;
case 0xC:
/* Longword virtual access with alt access mode (hw_ldl/a)*/