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authorBlue Swirl <blauwirbel@gmail.com>2011-05-21 07:10:23 +0000
committerBlue Swirl <blauwirbel@gmail.com>2011-06-26 18:25:31 +0000
commitf081c76ccfdbc1fdaa90fa5eb6abad46c1b5bfa8 (patch)
tree189b8a7a36be8eb52b8704c940b6ef328c18005b /target-alpha/cpu.h
parentf3e270377acd074f62e08960ef9444adf67d3590 (diff)
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-alpha/cpu.h')
-rw-r--r--target-alpha/cpu.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index e98b32513c..411bd55328 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -492,4 +492,26 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
}
#endif
+static inline bool cpu_has_work(CPUState *env)
+{
+ /* Here we are checking to see if the CPU should wake up from HALT.
+ We will have gotten into this state only for WTINT from PALmode. */
+ /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
+ asleep even if (some) interrupts have been asserted. For now,
+ assume that if a CPU really wants to stay asleep, it will mask
+ interrupts at the chipset level, which will prevent these bits
+ from being set in the first place. */
+ return env->interrupt_request & (CPU_INTERRUPT_HARD
+ | CPU_INTERRUPT_TIMER
+ | CPU_INTERRUPT_SMP
+ | CPU_INTERRUPT_MCHK);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+}
+
#endif /* !defined (__CPU_ALPHA_H__) */