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authorPeter Maydell <peter.maydell@linaro.org>2019-11-15 11:22:33 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-11-15 11:22:33 +0000
commit19bef037fe096b17edda103fd513ce6451da23c8 (patch)
treebc097d63bbc7de8d381198742e99443c32743612 /roms
parente10bf1fe00eceb2dbff973f5939036ef3f3c77a4 (diff)
parent6911fde41006b2afe3510755c4cff259ca56c1d9 (diff)
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc2' into staging
RISC-V Fixes for 4.2-rc2 This contains a handful of patches that I'd like to target for 4.2: * OpenSBI upgrade to 0.5 * Increase in the flash size of the virt board. * A non-functional cleanup. * A cleanup to our MIP handling that avoids atomics. This passes "make check" and boots OpenEmbedded for me. # gpg: Signature made Thu 14 Nov 2019 18:39:27 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.2-rc2: riscv/virt: Increase flash size opensbi: Upgrade from v0.4 to v0.5 target/riscv: Remove atomic accesses to MIP CSR remove unnecessary ifdef TARGET_RISCV64 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'roms')
m---------roms/opensbi0
1 files changed, 0 insertions, 0 deletions
diff --git a/roms/opensbi b/roms/opensbi
-Subproject ce228ee0919deb9957192d723eecc8aaae2697c
+Subproject be92da280d87c38a2e0adc5d3f43bab7b5468f0