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authorBlue Swirl <blauwirbel@gmail.com>2009-05-10 18:23:46 +0000
committerBlue Swirl <blauwirbel@gmail.com>2009-05-10 18:23:46 +0000
commitf0f26a06d51b7e7764f8951cdbf67ac9ad507f6d (patch)
tree7bfbaea41b559a929c803cd67ef87ad9eb049bd3 /qemu-tech.texi
parentd084469ca0a0fb7c7f51dbe9062092c6983dfa02 (diff)
downloadqemu-arm-f0f26a06d51b7e7764f8951cdbf67ac9ad507f6d.tar.gz
Update docs on dynamic condition code calculation
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'qemu-tech.texi')
-rw-r--r--qemu-tech.texi8
1 files changed, 5 insertions, 3 deletions
diff --git a/qemu-tech.texi b/qemu-tech.texi
index 6c24d910c3..ed2d35bf5e 100644
--- a/qemu-tech.texi
+++ b/qemu-tech.texi
@@ -363,7 +363,9 @@ look at @code{tcg/README}.
Lazy evaluation of CPU condition codes (@code{EFLAGS} register on x86)
is important for CPUs where every instruction sets the condition
codes. It tends to be less important on conventional RISC systems
-where condition codes are only updated when explicitly requested.
+where condition codes are only updated when explicitly requested. On
+Sparc64, costly update of both 32 and 64 bit condition codes can be
+avoided with lazy evaluation.
Instead of computing the condition codes after each x86 instruction,
QEMU just stores one operand (called @code{CC_SRC}), the result
@@ -376,8 +378,8 @@ conditional branches.
@code{CC_OP} is almost never explicitly set in the generated code
because it is known at translation time.
-The lazy condition code evaluation is used on x86, m68k and cris. ARM
-uses a simplified variant for the N and Z flags.
+The lazy condition code evaluation is used on x86, m68k, cris and
+Sparc. ARM uses a simplified variant for the N and Z flags.
@node CPU state optimisations
@section CPU state optimisations