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authorVictor CLEMENT <victor.clement@openwide.fr>2015-05-29 17:14:05 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2015-06-05 17:10:00 +0200
commitf1f4b57e88ff7c9cb20b074ff6106fd8f4397baa (patch)
tree7f46195c700eae2eb95f4cb37064b04cfd86c7f0 /qemu-options.hx
parent5045e9d912588a7421ab899ba510025722666fd1 (diff)
downloadqemu-arm-f1f4b57e88ff7c9cb20b074ff6106fd8f4397baa.tar.gz
icount: add sleep parameter to the icount option to set icount_sleep mode
The 'sleep' parameter sets the icount_sleep mode, which is enabled by default. To disable it, add the 'sleep=no' parameter (or 'nosleep') to the qemu -icount option. Signed-off-by: Victor CLEMENT <victor.clement@openwide.fr> Message-Id: <1432912446-9811-3-git-send-email-victor.clement@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'qemu-options.hx')
-rw-r--r--qemu-options.hx12
1 files changed, 10 insertions, 2 deletions
diff --git a/qemu-options.hx b/qemu-options.hx
index b3db6cbe86..85883f165a 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -3100,9 +3100,10 @@ re-inject them.
ETEXI
DEF("icount", HAS_ARG, QEMU_OPTION_icount, \
- "-icount [shift=N|auto][,align=on|off]\n" \
+ "-icount [shift=N|auto][,align=on|off][,sleep=no]\n" \
" enable virtual instruction counter with 2^N clock ticks per\n" \
- " instruction and enable aligning the host and virtual clocks\n", QEMU_ARCH_ALL)
+ " instruction, enable aligning the host and virtual clocks\n" \
+ " or disable real time cpu sleeping\n", QEMU_ARCH_ALL)
STEXI
@item -icount [shift=@var{N}|auto]
@findex -icount
@@ -3111,6 +3112,13 @@ instruction every 2^@var{N} ns of virtual time. If @code{auto} is specified
then the virtual cpu speed will be automatically adjusted to keep virtual
time within a few seconds of real time.
+When the virtual cpu is sleeping, the virtual time will advance at default
+speed unless @option{sleep=no} is specified.
+With @option{sleep=no}, the virtual time will jump to the next timer deadline
+instantly whenever the virtual cpu goes to sleep mode and will not advance
+if no timer is enabled. This behavior give deterministic execution times from
+the guest point of view.
+
Note that while this option can give deterministic behavior, it does not
provide cycle accurate emulation. Modern CPUs contain superscalar out of
order cores with complex cache hierarchies. The number of instructions