aboutsummaryrefslogtreecommitdiff
path: root/qapi-schema.json
diff options
context:
space:
mode:
authorEric Blake <eblake@redhat.com>2015-11-18 01:52:59 -0700
committerMarkus Armbruster <armbru@redhat.com>2015-12-17 08:21:28 +0100
commit86f4b6871c598e86f0542ed50d2ee5280fc66590 (patch)
treede07bfcbb9e0c05f23290a218e0976d354b12b66 /qapi-schema.json
parent04e0639d4e77b6d55491d396c8aa13929ee8ed9a (diff)
downloadqemu-arm-86f4b6871c598e86f0542ed50d2ee5280fc66590.tar.gz
cpu: Convert CpuInfo into flat union
The CpuInfo struct is used only by the 'query-cpus' output command, so we are free to modify it by adding fields (clients are already supposed to ignore unknown output fields), or by changing optional members to mandatory, while still keeping QMP wire compatibility with older versions of qemu. When qapi type CpuInfo was originally created for 0.14, we had no notion of a flat union, and instead just listed a bunch of optional fields with documentation about the mutually-exclusive choice of which instruction pointer field(s) would be provided for a given architecture. But now that we have flat unions and introspection, it is better to segregate off which fields will be provided according to the actual architecture. With this in place, we no longer need the fields to be optional, because the choice of the new 'arch' discriminator serves that role. This has an additional benefit: the old all-in-one struct was the only place in the code base that had a case-sensitive naming of members 'pc' vs. 'PC'. Separating these spellings into different branches of the flat union will allow us to add restrictions against future case-insensitive collisions, since that is generally a poor interface practice. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1447836791-369-25-git-send-email-eblake@redhat.com> [Spelling of CPUInfo{SPARC,PPC,MIPS} fixed] Signed-off-by: Markus Armbruster <armbru@redhat.com>
Diffstat (limited to 'qapi-schema.json')
-rw-r--r--qapi-schema.json120
1 files changed, 101 insertions, 19 deletions
diff --git a/qapi-schema.json b/qapi-schema.json
index 8b1a423fa7..f014a80f72 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -744,43 +744,125 @@
{ 'command': 'query-mice', 'returns': ['MouseInfo'] }
##
-# @CpuInfo:
+# @CpuInfoArch:
#
-# Information about a virtual CPU
+# An enumeration of cpu types that enable additional information during
+# @query-cpus.
+#
+# Since: 2.6
+##
+{ 'enum': 'CpuInfoArch',
+ 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
+
+##
+# @CpuInfoBase:
+#
+# Common information about a virtual CPU
#
# @CPU: the index of the virtual CPU
#
-# @current: this only exists for backwards compatible and should be ignored
+# @current: this only exists for backwards compatibility and should be ignored
#
# @halted: true if the virtual CPU is in the halt state. Halt usually refers
# to a processor specific low power mode.
#
# @qom_path: path to the CPU object in the QOM tree (since 2.4)
#
-# @pc: #optional If the target is i386 or x86_64, this is the 64-bit instruction
-# pointer.
-# If the target is Sparc, this is the PC component of the
-# instruction pointer.
-#
-# @nip: #optional If the target is PPC, the instruction pointer
-#
-# @npc: #optional If the target is Sparc, the NPC component of the instruction
-# pointer
-#
-# @PC: #optional If the target is MIPS, the instruction pointer
-#
# @thread_id: ID of the underlying host thread
#
+# @arch: architecture of the cpu, which determines which additional fields
+# will be listed (since 2.6)
+#
# Since: 0.14.0
#
# Notes: @halted is a transient state that changes frequently. By the time the
# data is sent to the client, the guest may no longer be halted.
##
-{ 'struct': 'CpuInfo',
+{ 'struct': 'CpuInfoBase',
'data': {'CPU': 'int', 'current': 'bool', 'halted': 'bool',
- 'qom_path': 'str',
- '*pc': 'int', '*nip': 'int', '*npc': 'int', '*PC': 'int',
- 'thread_id': 'int'} }
+ 'qom_path': 'str', 'thread_id': 'int', 'arch': 'CpuInfoArch' } }
+
+##
+# @CpuInfo:
+#
+# Information about a virtual CPU
+#
+# Since: 0.14.0
+##
+{ 'union': 'CpuInfo', 'base': 'CpuInfoBase', 'discriminator': 'arch',
+ 'data': { 'x86': 'CpuInfoX86',
+ 'sparc': 'CpuInfoSPARC',
+ 'ppc': 'CpuInfoPPC',
+ 'mips': 'CpuInfoMIPS',
+ 'tricore': 'CpuInfoTricore',
+ 'other': 'CpuInfoOther' } }
+
+##
+# @CpuInfoX86:
+#
+# Additional information about a virtual i386 or x86_64 CPU
+#
+# @pc: the 64-bit instruction pointer
+#
+# Since 2.6
+##
+{ 'struct': 'CpuInfoX86', 'data': { 'pc': 'int' } }
+
+##
+# @CpuInfoSPARC:
+#
+# Additional information about a virtual SPARC CPU
+#
+# @pc: the PC component of the instruction pointer
+#
+# @npc: the NPC component of the instruction pointer
+#
+# Since 2.6
+##
+{ 'struct': 'CpuInfoSPARC', 'data': { 'pc': 'int', 'npc': 'int' } }
+
+##
+# @CpuInfoPPC:
+#
+# Additional information about a virtual PPC CPU
+#
+# @nip: the instruction pointer
+#
+# Since 2.6
+##
+{ 'struct': 'CpuInfoPPC', 'data': { 'nip': 'int' } }
+
+##
+# @CpuInfoMIPS:
+#
+# Additional information about a virtual MIPS CPU
+#
+# @PC: the instruction pointer
+#
+# Since 2.6
+##
+{ 'struct': 'CpuInfoMIPS', 'data': { 'PC': 'int' } }
+
+##
+# @CpuInfoTricore:
+#
+# Additional information about a virtual Tricore CPU
+#
+# @PC: the instruction pointer
+#
+# Since 2.6
+##
+{ 'struct': 'CpuInfoTricore', 'data': { 'PC': 'int' } }
+
+##
+# @CpuInfoOther:
+#
+# No additional information is available about the virtual CPU
+#
+# Since 2.6
+#
+##
+{ 'struct': 'CpuInfoOther', 'data': { } }
##
# @query-cpus: