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author | Peter Maydell <peter.maydell@linaro.org> | 2017-01-09 14:04:25 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2017-01-09 14:04:25 +0000 |
commit | d64663e571e97c20b980004137f5720a10384d30 (patch) | |
tree | 678e6b89600f7c160351389b994db66280605fba /page_cache.c | |
parent | c051cb917dfe093070d8ec80f21b19805a46eee8 (diff) |
hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs
Implement the architecturally required traps from NS EL1
to EL2 for the CPU interface registers. These fall into
several different groups:
* group-0-only registers all trap if ICH_HRC_EL2.TALL0 is set
(exactly the registers covered by gicv3_fiq_access())
* group-1-only registers all trap if ICH_HRC_EL2.TALL1 is set
(exactly the registers covered by gicv3_irq_access())
* DIR traps if ICH_HCR_EL2.TC or ICH_HCR_EL2.TDIR are set
* PMR, RPR, CTLR trap if ICH_HCR_EL2.TC is set
* SGI0R, SGI1R, ASGI1R trap if ICH_HCR_EL2.TC is set or
if HCR_EL2.IMO or HCR_EL2.FMO are set
We split DIR and the SGI registers out into their own access
functions, leaving the existing gicv3_irqfiq_access() just
handling PMR, RPR and CTLR.
This commit doesn't implement support for trapping on
HSTR_EL2.T12 for the 32-bit registers, as we don't implement
any of those per-coprocessor trap bits currently and
probably will want to do those in some more centralized way.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'page_cache.c')
0 files changed, 0 insertions, 0 deletions