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authorPeter Maydell <peter.maydell@linaro.org>2021-02-04 17:03:27 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-02-15 13:15:14 +0000
commit86cee7ff0a95b0483534a12b15d17509180550db (patch)
tree073a68c87d277518347625e202e1da8fb5b773ff /include
parent909bfeb63f31977707b5a17820903cd839510088 (diff)
downloadqemu-arm-86cee7ff0a95b0483534a12b15d17509180550db.tar.gz
hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
The AN524 version of the SCC interface has different behaviour for some of the CFG registers; implement it. Each board in this family can have minor differences in the meaning of the CFG registers, so rather than trying to specify all the possible semantics via individual device properties, we make the behaviour conditional on the part-number field of the SCC_ID register which the board code already passes us. For the AN524, the differences are: * CFG3 is reserved rather than being board switches * CFG5 is a new register ("ACLK Frequency in Hz") * CFG6 is a new register ("Clock divider for BRAM") We implement both of the new registers as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/hw/misc/mps2-scc.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
index 514da49f69..49d070616a 100644
--- a/include/hw/misc/mps2-scc.h
+++ b/include/hw/misc/mps2-scc.h
@@ -29,7 +29,10 @@ struct MPS2SCC {
uint32_t cfg0;
uint32_t cfg1;
+ uint32_t cfg2;
uint32_t cfg4;
+ uint32_t cfg5;
+ uint32_t cfg6;
uint32_t cfgdata_rtn;
uint32_t cfgdata_out;
uint32_t cfgctrl;