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authorPeter Maydell <peter.maydell@linaro.org>2015-09-14 14:57:50 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-09-14 14:57:50 +0100
commit7e4804dafd4689312ef1172b549927a973bb5414 (patch)
tree8c1a23075f1fb0a3f435d5676bc89027b50237c3 /include/qemu/seqlock.h
parent2b750d9d261bda7f75b39dfc1e1e5f22502929d5 (diff)
parentf0d574d63f4603ec431f16ad535a555bf7548b94 (diff)
downloadqemu-arm-7e4804dafd4689312ef1172b549927a973bb5414.tar.gz
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150914' into staging
target-arm queue: * fix GIC region size in xlnx-zynqmp * xlnx-zynqmp: Remove unnecessary brackets * improve A64 generated TCG code * add GPIO devices to i.MX25 and i.MX31 * more missing pieces for EL2 support # gpg: Signature made Mon 14 Sep 2015 14:51:12 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20150914: (24 commits) target-arm: Add VMPIDR_EL2 target-arm: Break out mpidr_read_val() target-arm: Add VPIDR_EL2 target-arm: Suppress EPD for S2, EL2 and EL3 translations target-arm: Suppress TBI for S2 translations target-arm: Add VTTBR_EL2 target-arm: Add VTCR_EL2 hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully i.MX: Add GPIO devices to i.MX25 SOC i.MX: Add GPIO devices to i.MX31 SOC i.MX: Add GPIO device target-arm: Use tcg_gen_extrh_i64_i32 target-arm: Recognize ROR target-arm: Eliminate unnecessary zero-extend in disas_bitfield target-arm: Recognize UXTB, UXTH, LSR, LSL target-arm: Recognize SXTB, SXTH, SXTW, ASR target-arm: Implement fcsel with movcond target-arm: Implement ccmp branchless target-arm: Use setcond and movcond for csel target-arm: Handle always condition codes within arm_test_cc ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/qemu/seqlock.h')
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