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authorAtish Patra <atish.patra@wdc.com>2020-07-01 11:39:46 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-07-13 17:25:37 -0700
commit43cf723adca9a5e188c664c3b606a585192a599c (patch)
treeb9e8397567d10b3a4dc41640dec663b52a77be27 /include/hw
parent2c44bbf32cda5fbf85b697e3a12127f59d2c2e80 (diff)
downloadqemu-arm-43cf723adca9a5e188c664c3b606a585192a599c.tar.gz
riscv: Unify Qemu's reset vector code path
Currently, all riscv machines except sifive_u have identical reset vector code implementations with memory addresses being different for all machines. They can be easily combined into a single function in common code. Move it to common function and let all the machines use the common function. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-2-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/riscv/boot.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 9daa98da08..3e9759c89a 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -35,5 +35,7 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
+void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
+ hwaddr rom_size, void *fdt);
#endif /* RISCV_BOOT_H */