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authorPeter Maydell <peter.maydell@linaro.org>2020-11-30 17:07:34 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-02-15 13:16:13 +0000
commit60c860797d55cb3c90c4a77ba0610880e6404d0a (patch)
tree600eba6c8aa30579de848dafdd40096871a59c2b /include/hw
parentcc14bfc00362220c14082bcc8759863778b4ef0c (diff)
downloadqemu-arm-60c860797d55cb3c90c4a77ba0610880e6404d0a.tar.gz
hw/arm/armsse: Introduce SSE subsystem version property
We model Arm "Subsystems for Embedded" SoC subsystems using generic code which is split into various sub-devices which are configurable by QOM properties to handle the behaviour differences between the SSE subsystems we implement. Currently the only sub-device which needs to change is the IOTKIT_SYSCTL device, and we do this with a mix of properties that directly specify divergent behaviours (eg CPUWAIT_RST) and passing it the SYS_VERSION register value as a way for it to distinguish IoTKit from SSE-200. The "pass SYS_VERSION" approach is already a bit hacky, since the IOTKIT_SYSCTL device has to know that the different part of the register value happens to be bits [31:28]. For SSE-300 this register is renamed SOC_IDENTITY and has a different format entirely, all of whose fields can be configured by the SoC integrator when they integrate the SSE into their SoC, and so "pass SYS_VERSION" breaks down completely. Switch to using a simple integer property representing an internal-to-QEMU enumeration of the SSE flavour. For the moment we only need this in IOTKIT_SYSCTL, but as we add SSE-300 support a few of the other devices will also need to know. We define and permit a value for the SSE-300 so we can start using it in subsequent commits which add SSE-300 support. The now-redundant is_sse200 flag in IoTKitSysCtl will be removed in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- I didn't use a full-on qdev/QOM 'enum' property here because that requires messing with the QAPI schema, which seems like overkill for this entirely-internal-to-the-implementation bit of information passing.
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/arm/armsse-version.h42
-rw-r--r--include/hw/misc/iotkit-sysctl.h7
2 files changed, 45 insertions, 4 deletions
diff --git a/include/hw/arm/armsse-version.h b/include/hw/arm/armsse-version.h
new file mode 100644
index 0000000000..60780fa984
--- /dev/null
+++ b/include/hw/arm/armsse-version.h
@@ -0,0 +1,42 @@
+/*
+ * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
+ *
+ * Copyright (c) 2020 Linaro Limited
+ * Written by Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#ifndef ARMSSE_VERSION_H
+#define ARMSSE_VERSION_H
+
+
+/*
+ * Define an enumeration of the possible values of the sse-version
+ * property implemented by various sub-devices of the SSE, and
+ * a validation function that checks that a valid value has been passed.
+ * These are arbitrary QEMU-internal values (nobody should be creating
+ * the sub-devices of the SSE except for the SSE object itself), but
+ * we pick obvious numbers for the benefit of people debugging with gdb.
+ */
+enum {
+ ARMSSE_IOTKIT = 0,
+ ARMSSE_SSE200 = 200,
+ ARMSSE_SSE300 = 300,
+};
+
+static inline bool armsse_version_valid(uint32_t sse_version)
+{
+ switch (sse_version) {
+ case ARMSSE_IOTKIT:
+ case ARMSSE_SSE200:
+ case ARMSSE_SSE300:
+ return true;
+ default:
+ return false;
+ }
+}
+
+#endif
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index 2bc391138d..7cdafea3e2 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -17,9 +17,8 @@
* "system control register" blocks.
*
* QEMU interface:
- * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
- * system information block of the SSE
- * (used to identify whether to provide SSE-200-only registers)
+ * + QOM property "sse-version": indicates which SSE version this is part of
+ * (used to identify whether to provide SSE-200-only registers, etc)
* + sysbus MMIO region 0: the system information register bank
* + sysbus MMIO region 1: the system control register bank
*/
@@ -61,7 +60,7 @@ struct IoTKitSysCtl {
uint32_t pdcm_pd_sram3_sense;
/* Properties */
- uint32_t sys_version;
+ uint32_t sse_version;
uint32_t cpuwait_rst;
uint32_t initsvtor0_rst;
uint32_t initsvtor1_rst;