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authorPeter Maydell <peter.maydell@linaro.org>2017-02-16 09:37:36 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-20 14:22:39 +0000
commitc928c5ebec12c229304e983c02dd2f0168942c28 (patch)
treeee38ddda20864383ae517bdef4b0964783140b24 /include/hw/arm/armv7m.h
parent715004992705a44e23986fbc991e5214ed394e84 (diff)
downloadqemu-arm-c928c5ebec12c229304e983c02dd2f0168942c28.tar.gz
armv7m: QOMify the armv7m container
Create a proper QOM object for the armv7m container, which holds the CPU, the NVIC and the bitband regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/armv7m.h')
-rw-r--r--include/hw/arm/armv7m.h51
1 files changed, 51 insertions, 0 deletions
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
new file mode 100644
index 0000000000..193ad71b82
--- /dev/null
+++ b/include/hw/arm/armv7m.h
@@ -0,0 +1,51 @@
+/*
+ * ARMv7M CPU object
+ *
+ * Copyright (c) 2017 Linaro Ltd
+ * Written by Peter Maydell <peter.maydell@linaro.org>
+ *
+ * This code is licensed under the GPL version 2 or later.
+ */
+
+#ifndef HW_ARM_ARMV7M_H
+#define HW_ARM_ARMV7M_H
+
+#include "hw/sysbus.h"
+#include "hw/arm/armv7m_nvic.h"
+
+#define TYPE_BITBAND "ARM,bitband-memory"
+#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ MemoryRegion iomem;
+ uint32_t base;
+} BitBandState;
+
+#define TYPE_ARMV7M "armv7m"
+#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
+
+#define ARMV7M_NUM_BITBANDS 2
+
+/* ARMv7M container object.
+ * + Unnamed GPIO input lines: external IRQ lines for the NVIC
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
+ * + Property "cpu-model": CPU model to instantiate
+ * + Property "num-irq": number of external IRQ lines
+ */
+typedef struct ARMv7MState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+ NVICState nvic;
+ BitBandState bitband[ARMV7M_NUM_BITBANDS];
+ ARMCPU *cpu;
+
+ /* Properties */
+ char *cpu_model;
+} ARMv7MState;
+
+#endif