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authorPeter Maydell <peter.maydell@linaro.org>2021-01-14 14:07:29 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-02-15 14:10:07 +0000
commit6b1a3bf782d36be579cb3b38ad3a789e85275c03 (patch)
tree32fe18576eec56ccd3120bbffe603c1620ba5522 /hw
parenta0413c5db3175df585ca8abface8b8f8d4c2d045 (diff)
downloadqemu-arm-6b1a3bf782d36be579cb3b38ad3a789e85275c03.tar.gz
hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
The SSE uses 32 interrupts for its own devices, and then passes through its expansion IRQ inputs to the CPU's interrupts 33 and upward. Add a define for the number of IRQs the SSE uses for itself, instead of hardcoding 32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/arm/armsse.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 2b25fca1ca..5ae6ce344e 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -531,7 +531,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
int j;
char *gpioname;
- qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
+ qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
/*
* In real hardware the initial Secure VTOR is set from the INITSVTOR*
* registers in the IoT Kit System Control Register block. In QEMU
@@ -602,7 +602,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);
for (j = 0; j < s->exp_numirq; j++) {
- s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32);
+ s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS);
}
if (i == 0) {
gpioname = g_strdup("EXP_IRQ");