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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2014-01-06 10:16:38 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-01-08 19:07:21 +0000
commit1e77c91e2422ffa366fa5a0a39a6e7cc24a102ca (patch)
tree98b998a9df9144c72a99a36485deaa91e18e84d7 /hw
parent823dd48761a668c8e787cb9cf07234b656a05926 (diff)
char/cadence_uart: s/r_fifo/rx_fifo
Rename this field to match the many other uses of "rx". Xilinx docmentation (UG585) also refers to this as "RxFIFO". Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7386d7cee0ea175f7e53ed5ff045265528d34e32.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/char/cadence_uart.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 7edc1196f3..d6abc5b985 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -116,7 +116,7 @@ typedef struct {
MemoryRegion iomem;
uint32_t r[R_MAX];
- uint8_t r_fifo[RX_FIFO_SIZE];
+ uint8_t rx_fifo[RX_FIFO_SIZE];
uint32_t rx_wpos;
uint32_t rx_count;
uint64_t char_tx_time;
@@ -280,7 +280,7 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
s->r[R_CISR] |= UART_INTR_ROVR;
} else {
for (i = 0; i < size; i++) {
- s->r_fifo[s->rx_wpos] = buf[i];
+ s->rx_fifo[s->rx_wpos] = buf[i];
s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
s->rx_count++;
@@ -344,7 +344,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
if (s->rx_count) {
uint32_t rx_rpos =
(RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
- *c = s->r_fifo[rx_rpos];
+ *c = s->rx_fifo[rx_rpos];
s->rx_count--;
if (!s->rx_count) {
@@ -492,7 +492,7 @@ static const VMStateDescription vmstate_cadence_uart = {
.post_load = cadence_uart_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
- VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE),
+ VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
VMSTATE_UINT32(rx_count, UartState),
VMSTATE_UINT32(rx_wpos, UartState),
VMSTATE_TIMER(fifo_trigger_handle, UartState),