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authorMichael S. Tsirkin <mst@redhat.com>2011-11-21 18:57:50 +0200
committerAnthony Liguori <aliguori@us.ibm.com>2011-11-21 15:05:59 -0600
commitae392c416c69a020226c768d9c3af08b29dd6d96 (patch)
tree15c196cc1a091ae2e298ad580c2388ccd254e144 /hw
parent9a93b61730e3b46ef1c01ca522c6abe80ec13832 (diff)
msix: avoid mask updates if mask is unchanged
Check pending bit only if vector mask status changed. This is not really important for qemu.git but helps fix a bug in qemu-kvm.git. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/msix.c29
1 files changed, 20 insertions, 9 deletions
diff --git a/hw/msix.c b/hw/msix.c
index 29696016ad..149eed22fb 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -118,17 +118,25 @@ static void msix_clr_pending(PCIDevice *dev, int vector)
*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}
-static int msix_is_masked(PCIDevice *dev, int vector)
+static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
{
- unsigned offset =
- vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
- return dev->msix_function_masked ||
- dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
+ unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
+ return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
}
-static void msix_handle_mask_update(PCIDevice *dev, int vector)
+static bool msix_is_masked(PCIDevice *dev, int vector)
{
- if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
+ return msix_vector_masked(dev, vector, dev->msix_function_masked);
+}
+
+static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
+{
+ bool is_masked = msix_is_masked(dev, vector);
+ if (is_masked == was_masked) {
+ return;
+ }
+
+ if (!is_masked && msix_is_pending(dev, vector)) {
msix_clr_pending(dev, vector);
msix_notify(dev, vector);
}
@@ -166,7 +174,8 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
}
for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
- msix_handle_mask_update(dev, vector);
+ msix_handle_mask_update(dev, vector,
+ msix_vector_masked(dev, vector, was_masked));
}
}
@@ -176,14 +185,16 @@ static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
PCIDevice *dev = opaque;
unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
int vector = offset / PCI_MSIX_ENTRY_SIZE;
+ bool was_masked;
/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
if (vector >= dev->msix_entries_nr) {
return;
}
+ was_masked = msix_is_masked(dev, vector);
pci_set_long(dev->msix_table_page + offset, val);
- msix_handle_mask_update(dev, vector);
+ msix_handle_mask_update(dev, vector, was_masked);
}
static const MemoryRegionOps msix_mmio_ops = {