diff options
| author | Andrew Gacek <andrew.gacek@gmail.com> | 2016-12-27 14:59:23 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-12-27 14:59:23 +0000 |
| commit | 2494c9f6405a1979319f12d1bb4e9a6eb28a529d (patch) | |
| tree | 30a0cefc51a14f6f75850df37e6c03e562999e40 /hw | |
| parent | 450aaae8638e4c75ac6547ce6e09d63281a5a925 (diff) | |
cadence_uart: Check if receiver timeout counter is disabled
When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to
0, the receiver timeout counter should be disabled. See page 1801 of
"Zynq-7000 AP SoC Technical Reference Manual". This commit adds a
such a check before setting the receive timeout interrupt.
Signed-off-by: Andrew Gacek <andrew.gacek@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/char/cadence_uart.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index dba1c53586..4dcee571c0 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -138,9 +138,10 @@ static void fifo_trigger_update(void *opaque) { CadenceUARTState *s = opaque; - s->r[R_CISR] |= UART_INTR_TIMEOUT; - - uart_update_status(s); + if (s->r[R_RTOR]) { + s->r[R_CISR] |= UART_INTR_TIMEOUT; + uart_update_status(s); + } } static void uart_rx_reset(CadenceUARTState *s) |